This invention relates to computer systems, and more particularly to data transfer between buses.
In the design and development of ASICs (application specific integrated circuits) and FPGAs (field programmable gate arrays) maintaining high data bandwidth between buses which have different clock frequencies can prove problematic. Traditionally, to move data between a first bus having a clock speed which is higher than the clock speed of the second bus throttling or data pacing methods are used. Such a design is necessary because the bandwidth of the first bus is greater than the bandwidth of the second bus.
A system for maintaining data flow between buses is provided wherein the bandwidth of a first bus is less than the bandwidth of a second bus. The bandwidth of a bus is based on the clock speed of the bus and the bit width of the bus. The system includes a first bus having a first clock rate and a first bus-width, a second bus having a second clock rate and a second bus width, and control logic. The control logic receives data from the first bus and transfers the data to the second bus. The control logic may comprise a set of storage devices selectively coupled to the first bus and the set of storage devices may be addressable memory. The control logic may further include a first bus control logic for writing data to the set of storage devices and a second bus control logic for reading data from the set of storage devices. The data is written to the set of storage devices at the first clock rate of the first bus and read from the storage devices at the bus rate of the second bus.
In another embodiment, a flag bit which is coupled to the set of storage devices and is set when the set of storage devices is written to. The flag bit for a storage device provides indicia that the storage device is filled with data. In yet another embodiment, the system includes a multiplexor for selection of a path between the first bus and one storage device of the set of storage devices. The system also includes a demultiplexor for selecting a path between one storage device from the set of storage devices and the second bus.
In any of the embodiments the bus width of the second bus is a multiple of the bus width of the first bus. Additionally, the clock rate of the first bus is greater than the clock rate of the second bus. In still another embodiment, the set of storage devices comprises two or more sets of storage devices which may be written to in parallel.